Computer Architecture
How CPUs, memory, and I/O are organized — instruction sets, pipelines, caches, and the design of whole computers.
Computer architecture is the bridge between hardware and software. It studies how instruction sets, pipelines, caches, and memory hierarchies are designed and how they constrain everything above them.
Core
The essentials. Start here.-
Cache
Small, fast memory close to the CPU that keeps recently or about-to-be-used data, hiding the slowness of main memory.
core intermediate concept -
CPU Pipeline
An assembly-line technique for executing instructions — split each instruction into stages and overlap many in flight at once.
core intermediate concept -
Instruction Set
The contract between a CPU and the programs that run on it — the menu of operations a processor can perform.
core intermediate concept -
Register
A handful of tiny, lightning-fast storage cells inside the CPU — the only memory most instructions actually read from or write to.
core intermediate concept
Important
What you'll meet next.-
DMA
Direct Memory Access — hardware that lets devices transfer data to and from main memory without routing every byte through the CPU, freeing the processor for other work.
intermediate concept -
Memory Hierarchy
The layered set of storage in a computer — from registers to disk — trading size for speed.
intermediate concept -
RISC vs CISC
Two philosophies of CPU instruction set design — Reduced Instruction Set Computing (small, simple, fast) versus Complex Instruction Set Computing (rich, do-more-per-instruction).
intermediate concept -
Branch Prediction
A CPU technique that guesses the outcome of a branch (an if or a loop) before it's actually known, so the pipeline can keep executing instead of stalling — and rolls back if the guess was wrong.
advanced concept -
Cache Coherence
The set of protocols that keep multiple CPU caches in sync so all cores see a consistent view of memory.
advanced concept -
Out-of-Order Execution
A CPU technique that executes instructions as soon as their inputs are ready rather than in strict program order, keeping execution units busy while slow operations like memory loads complete.
advanced concept -
SIMD
Single Instruction, Multiple Data — a CPU feature that applies one operation to many data elements at once, accelerating the vector and array math common in graphics, media, and machine learning.
advanced concept
Supplemental
Niche, historical, or specialized.-
ARM vs x86
The two dominant CPU instruction set architectures — x86 (complex, high-performance, dominant in PCs and servers) and ARM (power-efficient, dominant in mobile and increasingly in servers and laptops) — with fundamentally different design philosophies converging in practice.
supplemental intermediate concept -
Speculative Execution
A CPU technique that executes instructions before knowing whether they will be needed — predicting branches and precomputing results to keep execution units busy, with disastrous security consequences when exploited by Spectre-class attacks.
supplemental advanced concept -
Superscalar Execution
A CPU design that issues multiple independent instructions per clock cycle by maintaining several execution units in parallel — extracting instruction-level parallelism (ILP) from sequential code automatically.
supplemental advanced concept -
Systolic Array
A grid of simple processing elements that pass data between neighbours in a rhythmic, pipelined fashion — used in neural network accelerators (Google TPU) to perform dense matrix multiplications with extreme efficiency.
supplemental advanced concept -
TLB
A small, fast cache for virtual-to-physical address translations — avoiding the costly page table walk on every memory access and making virtual memory practical at CPU speed.
supplemental advanced concept